Computer Organization and Architecture MCQ Answers

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Computer Organization and Architecture MCQ Answers

This is the computer organization and architecture mcq with 100% correct answers:

Q1. The drawback of building a large memory with DRAM is ______________

1. The Slow speed of operation
2. The large cost factor
3. The inefficient memory organization
4. All of the mentioned

Q2. In a 4K-bit chip organization has a total of 19 external connections, then it has _______ address if 8 data lines are there.

1. 10
2. 12
3. 9
4. 8

Q3. What does ISO stands for?

1. International Software Organization
2. Industrial Software Organization
3. International Standards Organization
4. Industrial Standards Organization

Q4. The bit used to signify that the cache location is updated is ________

1. Flag bit
2. Reference bit
3. Update bit
4. Dirty bit

Q5. During a write operation if the required block is not present in the cache then ______ occurs.

1. Write miss
2. Write latency
3. Write hit
4. Write delay

Q6. While using the direct mapping technique, in a 16 bit system the higher order 5 bits are used for ________

1. Id
2. Word
3. Tag
4. Block

Q7. The bit used to indicate whether the block was recently used or not is _______

1. Reference bit
2. Dirty bit
3. Control bit
4. Idol bit

Q8. The number successful accesses to memory stated as a fraction is called as _____

1. Access rate
2. Success rate
3. Hit rate
4. Miss rate

Q9. To reduce the memory access time we generally make use of ______

1. SDRAM’s
2. Heaps
3. Cache’s
4. Higher capacity RAM’s

Q10. The IA-32 system follows which of the following design?

1. CISC
2. SIMD
3. RISC
4. None of the mentioned

Q11. Which of the following architecture is suitable for a wide range of data types?

1. IA-32
2. ARM
3. ASUS firebird
4. 68000

Q12. In IA-32 architecture along with the general flags, which of the following conditional flags are provided?

1. TF
2. IOPL
3. IF
4. All of the mentioned

Q13. The VLIW architecture follows _____ approach to achieve parallelism.

1. SISD
2. MIMD
3. MISD
4. SIMD

Q14. What does VLIW stands for?

1. Very Long Instruction Width
2. Very Large Instruction Word
3. Very Long Instruction Width
4. Very Long Instruction Word

Q15. In CISC architecture most of the complex instructions are stored in _____

1. CMOS
2. Register
3. Transistors
4. Diodes

Q16. Both the CISC and RISC architectures have been developed to reduce the ______

1. Time delay
2. Semantic gap
3. Cost
4. All of the mentioned

Q17. ________ are the different type/s of generating control signals.

1. Hardwired
2. Micro-instruction
3. Micro-programmed
4. Both Micro-programmed and Hardwired

Q18. If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value of S is (Where S is term of the Basic performance equation..

1. 2
2. ~1
3. ~7
4. 2

Q19. The small extremely fast, RAM’s all called as ________

1. Heaps
2. Accumulators
3. Stacks
4. Cache

Q20. For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster execution?

1. ANSA
2. Super-scalar
3. ISA
4. All of the mentioned

Q21. What is the full form of ISA?

1. Industry Standard Architecture
2. International Standard Architecture
3. International American Standard
4. None of the mentioned

Q22. Which of the following is the full form of CISC?

1. Complex Instruction Sequential Compilation
2. Complete Instruction Sequential Compilation
3. Computer Integrated Sequential Compiler
4. Complex Instruction Set Computer

Q23. The reason for the cells to lose their state over time is ________

1. Use of Shift registers
2. The lower voltage levels
3. Usage of capacitors to store the charge
4. None of the mentioned

Q24. In order to read multiple bytes of a row at the same time, we make use of ______

1. Memory extension
2. Cache
3. Shift register
4. Latch

Q25. The difference in the address and data connection between DRAM’s and SDRAM’s is _______

1. The requirement of more address lines in SDRAM’s
2. The usage of a buffer in SDRAM’s
3. The usage of more number of pins in SDRAM’s
4. None of the mentioned

Q26. The chip can be disabled or cut off from an external connection using ______

1. ACPT
2. RESET
3. LOCK
4. Chip select

Q27. The controller multiplexes the addresses after getting the _____ signal.

1. INTR
2. ACK
3. RESET
4. Request

Q28. The data is transferred over the RAMBUS as _______

1. Blocks
2. Swing voltages
3. Bits
4. Packets

Q29. The memory devices which are similar to EEPROM but differ in the cost effectiveness is ______

1. CMOS
2. Memory sticks
3. Blue-ray devices
4. Flash memory

Q30. The flash memory modules designed to replace the functioning of a hard disk is ______

1. RIMM
2. FIMM
3. Flash drives
4. DIMM

Q31. What is computer architecture?

1. set of categories and methods that specify the functioning, organization, and implementation of computer systems
2. set of principles and methods that specify the functioning, organization, and implementation of computer systems
3. set of functions and methods that specify the functioning, organization, and implementation of computer systems
4. None of the mentioned

Q32. What is computer organization?

1. structure and behavior of a computer system as observed by the user
2. structure of a computer system as observed by the developer
3. structure and behavior of a computer system as observed by the developer
4. All of the mentioned

Q33. Which of the following is a type of computer architecture?

1. Microarchitecture
2. Harvard Architecture
3. Von-Neumann Architecture
4. All of the mentioned

Q34. Which of the following is a type of architecture used in the computers nowadays?

1. Microarchitecture
2. Harvard Architecture
3. Von-Neumann Architecture
4. System Design

Q35. Which of the following is the subcategories of computer architecture?

1. Microarchitecture
2. Instruction set architecture
3. Systems design
4. All of the mentioned

Q36. Which of the architecture is power efficient?

1. RISC
2. ISA
3. IANA
4. CISC

Q37. What does CSA stands for?

1. Computer Service Architecture
2. Computer Speed Addition
3. Carry Save Addition
4. None of the mentioned

Q38. If an exception is raised and the succeeding instructions are executed completely, then the processor is said to have ______

1. Generation word
2. Exception handling
3. Imprecise exceptions
4. None of the mentioned

Also Read: Data Structure MCQ Answers

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